1. Field of the Invention
The invention is related to the field of packet communications, and in particular, to packet processing circuitry.
2. Statement of the Problem
A communication packet is a unit of information that is transferred from one point to another over a communication system. The packet includes a header that indicates to the communication system how the packet should be processed. The primary task when processing a packet is properly routing the packet from the sender to the receiver, although there are many other tasks, such as security, service classification, billing, and address translation. Two common examples of packet communication protocols are the Internet Protocol (IP) and the Asynchronous Transfer Mode (ATM) protocol.
Communication packet processors are integrated circuits that receive, process, and transmit packets. With an insatiable demand for high-speed communications, packet processors are being driven to handle more packets at higher speeds. Compounding the problem is the desire that packet processors offer a more robust set of packet handling options.
To accomplish this difficult task, a packet processor includes a high-speed core processor that executes a packet processing software application. Under software control, the core processor processes the header of an incoming packet to retrieve context information from a memory for the packet. The context information specifies how the packet should be handled with respect to routing, security, and other areas. Under software control, the core processor then processes the context information to control packet handling.
To retrieve the desired context information, the core processor must associate the packet header with the memory locations that hold the desired context information. The core processor must then retrieve the desired context information from the associated memory locations. If the core processor modifies the context information, it must then write the modified context information back to the correct memory locations. This process is repeated for each packet, so the core processor is repeatedly associating headers with memory locations, retrieving context information, and writing modified context information to the memory locations.
This task is further complicated by the increase in processing options that can be applied to a packet. As the processing options increase, so does the size of the context information that specifies these options. The core processor must now handle increasingly larger amounts of context information, or the core processor must selectively retrieve only the desired data contained in the context information.
With increasing speeds and processing requirements, the core processor is becoming over-tasked. The result is either a loss of speed or processing options. One solution is simply to add higher-speed processors. Unfortunately, this solution adds too much cost to the underlying system.
A Content-Addressable Memory (CAM) is an integrated circuit that can search a list at high speed to provide a corresponding result. The CAM is configured with a list of selector entries. Each selector entry has a corresponding result. When the CAM receives an input selector, it searches the list of selector entries for a match. The search is accomplished at high speed by concurrently comparing each selector entry to the input selector. Unfortunately, CAMs have not been effectively applied to help solve the above problem.